Silicon Labs /EFR32FG23B010F512IM40 /RAC_NS /PATRIM3

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Interpret as PATRIM3

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (bleed_0uA)TXTRIMDREGBLEED 0 (disable)TXTRIMDREGBLEEDAUTO 0 (disable_bleed_auto)TXTRIMOREGBLEEDAUTO 0 (v1p222)TXTRIMDREGFB 0 (v1p340)TXTRIMOREGFB 0 (v1p212)TXTRIMDREG 0 (v1p420)TXTRIMOREG 0 (v1p354)TXTRIMRREG 0 (disable_psrr_boost)TXTRIMDREGPSR 0 (disable_psrr_cancellation)TXTRIMOREGPSR 0 (slice_1x)TXTRIMDREGSLICES 0 (enable_oreg)TXTRIMOREGSLICES 0 (disable_extra_bw)TXTRIMDREGMOREBW 0 (disable)TXTRIMOREGMOREBW

TXTRIMOREGBLEEDAUTO=disable_bleed_auto, TXTRIMDREG=v1p212, TXTRIMDREGBLEED=bleed_0uA, TXTRIMOREG=v1p420, TXTRIMOREGSLICES=enable_oreg, TXTRIMDREGBLEEDAUTO=disable, TXTRIMRREG=v1p354, TXTRIMDREGMOREBW=disable_extra_bw, TXTRIMOREGMOREBW=disable, TXTRIMDREGSLICES=slice_1x, TXTRIMOREGPSR=disable_psrr_cancellation, TXTRIMDREGPSR=disable_psrr_boost, TXTRIMOREGFB=v1p340, TXTRIMDREGFB=v1p222

Description

No Description

Fields

TXTRIMDREGBLEED

TXTRIMDREGBLEED

0 (bleed_0uA): undefined

1 (bleed_140uA): undefined

2 (bleed_280uA): undefined

3 (bleed_420uA): undefined

TXTRIMDREGBLEEDAUTO

TXTRIMDREGBLEEDAUTO

0 (disable): undefined

1 (enable): undefined

TXTRIMOREGBLEEDAUTO

TXTRIMOREGBLEEDAUTO

0 (disable_bleed_auto): undefined

1 (enable_bleed_auto): undefined

TXTRIMDREGFB

TXTRIMDREGFB

0 (v1p222): undefined

1 (v1p276): undefined

2 (v1p346): undefined

3 (v1p436): undefined

TXTRIMOREGFB

TXTRIMOREGFB

0 (v1p340): undefined

1 (v1p491): undefined

2 (v1p641): undefined

3 (v1p791): undefined

4 (v1p941): undefined

5 (v2p091): undefined

6 (v2p241): undefined

7 (v2p391): undefined

8 (v2p541): undefined

9 (v2p691): undefined

10 (v2p841): undefined

11 (v2p991): undefined

12 (v3p141): undefined

TXTRIMDREG

TXTRIMDREG

0 (v1p212): undefined

1 (v1p257): undefined

2 (v1p301): undefined

3 (v1p346): undefined

4 (v1p391): undefined

5 (v1p436): undefined

6 (v1p481): undefined

7 (v1p526): undefined

TXTRIMOREG

TXTRIMOREG

0 (v1p420): undefined

1 (v1p448): undefined

2 (v1p475): undefined

3 (v1p503): undefined

4 (v1p531): undefined

5 (v1p558): undefined

6 (v1p586): undefined

7 (v1p613): undefined

8 (v1p641): undefined

9 (v1p668): undefined

10 (v1p696): undefined

11 (v1p723): undefined

12 (v1p751): undefined

13 (v1p778): undefined

14 (v1p806): undefined

15 (v1p833): undefined

TXTRIMRREG

TXTRIMRREG

0 (v1p354): undefined

1 (v1p380): undefined

2 (v1p406): undefined

3 (v1p432): undefined

4 (v1p458): undefined

5 (v1p484): undefined

6 (v1p510): undefined

7 (v1p536): undefined

8 (v1p562): undefined

9 (v1p588): undefined

10 (v1p614): undefined

11 (v1p640): undefined

12 (v1p666): undefined

13 (v1p692): undefined

14 (v1p707): undefined

15 (v1p708): undefined

TXTRIMDREGPSR

TXTRIMDREGPSR

0 (disable_psrr_boost): undefined

1 (enable_psrr_boost): undefined

TXTRIMOREGPSR

TXTRIMOREGPSR

0 (disable_psrr_cancellation): undefined

1 (enable_psrr_cancellation): undefined

TXTRIMDREGSLICES

TXTRIMDREGSLICES

0 (slice_1x): undefined

1 (slice_2x): undefined

2 (slice_3x): undefined

3 (slice_4x): undefined

TXTRIMOREGSLICES

TXTRIMOREGSLICES

0 (enable_oreg): undefined

1 (not_valid1): undefined

2 (not_valid2): undefined

3 (not_valid3): undefined

TXTRIMDREGMOREBW

TXTRIMDREGMOREBW

0 (disable_extra_bw): undefined

1 (enable_extra_bw): undefined

TXTRIMOREGMOREBW

TXTRIMOREGMOREBW

0 (disable): undefined

1 (enable): undefined

Links

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